Modern digital devices require large amounts of memory. In order to pack large amounts of memory into a small package, semiconductor manufacturers have stacked integrated circuit chips within a single package. Wire bonding techniques are used to interconnect integrated circuits stacked within the same package. However, the wire bonding of stacked structures is difficult, and thus expensive, for stacks of larger numbers of chips. Furthermore, providing wire bonding to the chips after stacking makes it difficult to test each integrated circuit layer before stacking. Failure to test individual chip layers before assembly often results in an unacceptably low yield rate in the final stacked package.
In order to improve yield and thereby reduce manufacturing cost of stacks including large numbers of chips, the industry has adopted the practice of packaging and testing each chip before stacking. The defective chips are eliminated before stacking into a final stacked chip assembly. In order to facilitate testing, chips are packaged into thin testable packages, or “paper-thin packages.” In order to stack as many integrated circuit layers as possible per unit volume, each layer is kept as thin as possible. Thus chips have been thinned to thicknesses as low as 75 micrometers in production, and 35 micrometers in developmental prototypes. Chip thickness now represents less than half of the total thickness of a stacked package; thus integrated circuit chip thickness is no longer the limiting factor that determines package thickness. Instead, interconnections represent the major factor limiting package thickness.
The most common stacking interconnection is a ball stack as described in U.S. Pat. No. 5,783,870 entitled “Method of Connecting Packages of a Stacked Ball Array Structure”. In a ball stack, solder balls are placed along the periphery of the package. A solderable contact pad is located above each solder ball. Each solder ball is typically between 0.3 to 0.5 mm in diameter. The ball height should be large enough to reliably accommodate any thermal expansion mismatches between the materials. Making ball diameters substantially smaller than 0.3 mm increases ball cracking and failure rates due to thermally activated mechanical stress.
Assuming a minimum ball size of 0.3 mm and a thin core printed wiring board of approximately 0.15 mm results in each ball stack package having a height of around 0.4–0.5 mm. An eight high stack of chips is typically around 3.6 mm high. Current design objectives target 1.2 mm as a maximum height for any stacked package as determined by the size of the electronic system. In order to fit within the 1.2 mm required height, each layer of an eight layer stack is typically no higher than 0.15 mm.
A second problem with ball stack systems results from the elevated temperatures used to melt the balls and attach the layers. These elevated temperatures result in package flow and deformation problems. During solder attach of a conventional stacked package assembly, the solder balls in the stack melt and allow the stack of individually packaged chips to move.
Other packaging techniques have been described such as microelectronic spring contacts as described in U.S. Pat. No. 6,627,980 B2 entitled “Stacked Semiconductor Device Assembly With Microelectronic Spring Contacts.” However, the described stacking techniques are not laterally compact due to factors such as staggered stacking.
Thus a new method of interconnecting stacked integrated circuit layers is needed.